1. Field of the Invention
The present invention relates to a method and system for digital signal processing, and more specifically for synchronizing, controlling and monitoring a group of processors arranged as a cascade of processing stages.
2. Description of Related Art
Many tasks in real-time signal processing systems are systolic in nature. That is, digitized samples of a signal source sampled at a regular interval are to be processed sequentially. An example of the processing may be to filter the original signal in some desired way. Typically, each digital signal sample word fed into the filter results in the production of a corresponding filtered sample. The arrival of the sample forms the "pulse" of the system, giving rise to the term systolic. Typically, it may be necessary to process dozens or hundreds of signal sources simultaneously. Usually, the samples for a given time instant are grouped together to form a packet of digital words. For the case of many signal channels, at each sample time a packet of sample words are processed rather than a single sample word. Given the finite processing capability of a given processor, it often becomes necessary to employ many processors operating together to achive the required number of computations per second.
A particularly useful way of arranging the many processors is to organize them as cascaded groups of processors, with each group forming a stage operating within the same time period. The outputs of a given stage form the inputs to the succeeding stage. The total processing task is decomposed into a finite set of sequential operations. This is called pipelining. These tasks are distributed over the stages of processor array. Thus, an output sample corresponding to a given input sample will appear at the end of the chain with a fixed time delay corresponding to the number of stages multiplied by the sampling period. All processing for a given stage must be completed within the time period between samples.
Typically there will be one input processor which accepts the input packet and one output processor which produces an output packet. However, based on data volume and arrival rates, there may be more than one input processor and more than one output processor. A simple example, based on digital signal processors ("DSPs") that can accept up to two inputs and can supply up to two outputs, is the case of a 5 stage, 10 processor array which is arranged in a 1-2-4-2-1 processor configuration.
For distributed systolic systems, the efficiency of computation directly determines how many processing cycles per processor per second are possible. This determines how many processors are required.
Often, in order to maximize the efficiency of the systolic processor it is necessary to organize the contents of the incoming packet in special ways. Unfortunately, past systems typically have used a fixed packet structure in which the samples of the packet have not been organized with computing efficiency in mind. As processing demands change over time (in response to operator changes) the fixed arrangement causes a loss of efficiency.
A common problem in such multi-stage, packet-based systolic processors is the need to communicate with and monitor the function of each of the possibly hundreds of processors. Such communication is needed, for example, to change filter parameters in order to adaptively filter a signal over a long time interval or to otherwise process samples in response to an operator's needs. As processing proceeds, it may also be necessary to determine if the specified filtering is proceeding smoothly or if the operation of the processors are operating correctly. In order to debug a complex systolic array, it is necessary to be able to verify the actions of each processor. It can be prohibitively expensive or complex to attempt to provide a communication channel from each signal processor element to a centralized control processor.